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PCF8576CU/2 Datasheet(PDF) 33 Page - NXP Semiconductors

Part # PCF8576CU/2
Description  Universal LCD driver for low multiplex rates
PDF  56 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF8576CU/2 Datasheet(HTML) 33 Page - NXP Semiconductors

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PCF8576C_9
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 09 — 9 July 2009
33 of 56
NXP Semiconductors
PCF8576C
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
[1]
fclk < 125 kHz, I2C-bus maximum transmission speed is derated.
[2]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
Table 20.
Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Timing characteristics: driver timing waveforms (see Figure 27)
fclk
clock frequency
[1]
normal mode; VDD = 5 V 125
200
315
kHz
power saving mode;
VDD =3 V
21
31
48
kHz
tclk(H)
clock HIGH time
1
-
-
µs
tclk(L)
clock LOW time
1
-
-
µs
tPD(SYNC_N) SYNC propagation delay
-
-
400
ns
tSYNC_NL
SYNC LOW time
1
-
-
µs
tPD(drv)
driver propagation delay
VLCD = VDD − 5 V
-
-
30
µs
Timing characteristics: I2C-bus (see Figure 28)
[2]
tBUF
bus free time between a STOP and START
condition
4.7
-
-
µs
tHD;STA
hold time (repeated) START condition
4.0
-
-
µs
tSU;STA
set-up time for a repeated START condition
4.7
-
-
µs
tLOW
LOW period of the SCL clock
4.7
-
-
µs
tHIGH
HIGH period of the SCL clock
4.0
-
-
µs
tr
rise time of both SDA and SCL signals
-
-
1
µs
tf
fall time of both SDA and SCL signals
-
-
0.3
µs
Cb
capacitive load for each bus line
-
-
400
pF
tSU;DAT
data set-up time
250
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP condition
4.0
-
-
µs



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