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STM32F101X4 Datasheet(PDF) 57 Page - STMicroelectronics |
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STM32F101X4 Datasheet(HTML) 57 Page - STMicroelectronics |
57 / 73 page STM32F101x4, STM32F101x6 Electrical characteristics Doc ID 15058 Rev 3 57/74 SPI interface characteristics Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 8. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40. SPI characteristics(1) 1. Remapped SPI characteristics to be determined. Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode 0 18 MHz Slave mode 0 18 tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF 8 ns tsu(NSS) (2) 2. Based on characterization, not tested in production. NSS setup time Slave mode 4 tPCLK th(NSS) (2) NSS hold time Slave mode 73 tw(SCKH) (2) tw(SCKL) (2) SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 60 tsu(MI) (2) Data input setup time Master mode SPI 1 tsu(SI) (2) Data input setup time Slave mode 1 th(MI) (2) Data input hold time Master mode SPI 1 th(SI) (2) Data input hold time Slave mode 3 ta(SO) (2)(3) 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. Data output access time Slave mode, fPCLK = 36 MHz, presc = 4 055 Slave mode, fPCLK = 24 MHz 0 4 tPCLK tdis(SO) (2)(4) 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Data output disable time Slave mode 10 tv(SO) (2)(1) Data output valid time Slave mode (after enable edge) 25 tv(MO) (2)(1) Data output valid time Master mode (after enable edge) 3 th(SO) (2) Data output hold time Slave mode (after enable edge) 25 th(MO) (2) Master mode (after enable edge) 4 |
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