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AT697F Datasheet(PDF) 132 Page - ATMEL Corporation |
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AT697F Datasheet(HTML) 132 Page - ATMEL Corporation |
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132 / 155 page ![]() 132 7703C–AERO–6/09 AT697F ADVANCE INFORMATION Maximum Skew Test Conditions • Maximum Skew Programmed • Temperature range : -55°C to 125°C • Voltage range : – I/O: 3,3V +/- 0,30V – Core: 1,8V +/- 0,15V • Output load : 30pF Table 127. AC Characteristics - Maximum Skew Parameter Min (ns) Max (ns) Comment Reference edge (‘+’ for rising edge) t1 11 CLK Period with PLL disable t1_p 44 57 CLK Period with PLL enable t2 4.95 CLK Low and High pulse width - PLL disabled t2_p 20 CLK Low and High pulse width - PLL enabled t3 11 SDCLK Period t4 3.5 7 SDCLK output delay - PLL disabled CLK t5 1.107 PLL setup time t6 1*t3 Reset Pulse Width t10 1.5 8 A[27:0] output delay SDCLK + t11 1.5 9 D[31:0] and CB[7:0] output delay SDCLK + t12 4 D[31:0] and CB[7:0] setup time SDCLK + t13 0 D[31:0] and CB[7:0] hold time SDCLK + t14 D[31:0] and CB[7:0] hold time during write SDCLK + t15 1.5 8.5 OE*, READ and WRITE* output delay SDCLK + t16 1.5 6.5 ROMS*[1:0] output delay SDCLK + t17 7 RAMS*[4:0], RAMOE*[4:0] and RWE*[3:0] output delay SDCLK + t18 1.5 6.5 IOS* output delay SDCLK + t19 5 BRDY* setup time SDCLK + t20 0 BRDY* hold time SDCLK + t21 3 9.5 SDCAS* output delay SDCLK + t22 3 9.5 SDCS*[1:0], SDRAS*, SDWE* and SDDQM*[3:0] output delay SDCLK + t23 6 BEXC* setup time SDCLK + t24 0 BEXC* hold time SDCLK + t25 2.5 9 PIO[15:0] output delay SDCLK + t26 6 PIO[15:0] setup time SDCLK + t27 0 PIO[15:0] hold time SDCLK + t28 PIO[15:0] hold time during write SDCLK + t101 30 PCI_CLK period t102 13.5 PCI_CLK low and high pulse width |
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