ST7632 datasheet(22/96 Pages) SITRONIX

22 / 96 page

ST7632

Ver 1.7

22/96

2006/08/15

7-2 ACCESS TO DDRAM AND INTERNAL REGISTERS

ST7632 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus

holder attached to the internal, requiring the cycle time alone without needing the wait time.

For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the

DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is

dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus

in the succeeding read cycle. Fig. 7.2.1 illustrates these relations.

D(N)

D(N+1) D(N+2)

D(N+3)

D(N)

D(N+1)

D(N+2)

D(N+3)

N+1

N+2

N+3

MPU signal

/WR

DATA

Internal signals

/WR

BUS HOLDER

COLUMN ADDRESS

Write

Operation

Dummy

D(N)

D(N+1)

MPU signal

/WR

DATA

Internal signals

/WR

COLUMN ADDRESS

/RD

D(N)

D(N+1)

D(N+2)

D(N)

D(N+1)

D(N+2)

/RD

BUS HOLDER

Read

Operation

Fig 7.2.1

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