DM9013 datasheet(49/75 Pages) DAVICOM

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DM9013

3-port switch with Processor Interface

Preliminary datasheet

DM9013-15-DS-P03

April 9, 2009

1 = Force 100Mbps good link status

This bit is useful for diagnostic purposes

Reserved

0, RW

Reserved

Force to 0 in application.

COL_LED

0, RW

COL LED Control (valid in PHY test mode)

RPDCTR-EN

1, RW

Reduced Power Down Control Enable

This bit is used to enable automatic reduced power down

0 = Disable automatic reduced power down

1 = Enable automatic reduced power down

SMRST

0, RW

Reset State Machine

When writes 1 to this bit, all state machines of PHY will be reset.

This bit is self-clear after reset is completed

MFPSC

1, RW

MF Preamble Suppression Control

MII frame preamble suppression control bit

0 = MF preamble suppression bit off

1 = MF preamble suppression bit on

SLEEP

0, RW

Sleep Mode

Writing a 1 to this bit will cause PHY entering the Sleep mode and

power down all circuit except oscillator and clock generator circuit.

When waking up from Sleep mode (write this bit to 0), the

configuration will go back to the state before sleep; but the state

machine will be reset

RLOUT

0, RW

Remote Loop out Control

When this bit is set to 1, the received data will loop out to the

transmit channel. This is useful for bit error rate testing

DM9013 Datasheet(PDF) 49 Page - Davicom Semiconductor, Inc.

DM9013 Datasheet(HTML) 49 Page - Davicom Semiconductor, Inc.

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