DM9102DEP datasheet(37/70 Pages) DAVICOM

37 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

Write as 0, ignore on read

PDF

0, RO/LH Local Device Parallel Detection Fault:

PDF=1: A fault detected via parallel detection function.

PDF=0: No fault detected via parallel detection function

LP_NP_ABLE

0, RO

Link Partner Next Page Able:

LP_NP_ABLE=1: Link partner, next page available

LP_NP_ABLE=0: Link partner, no next page

NP_ABLE

0,RO/P

Local Device Next Page Able:

NP_ABLE=1: DM9102D, next page available

NP_ABLE=0: DM9102D, no next page

DM9102D does not support this function, so this bit is always 0.

PAGE_RX

0, RC/LH

New Page Received:

A new link of code-word page received. This bit will be automatically cleared

when the register (Register 6) is read by management.

LP_AN_ABLE

0, RO

Link Partner Auto-negotiation Able:

A “1” in this bit indicates that the link partner supports Auto-negotiation.

6.3.8 DAVICOM Specified Configuration Register (DSCR) – 10H

Bit

Name

Default

Description

BP_4B5B

0,RW

Bypass 4B5B Encoding and 5B4B Decoding

1 = 4B5B encoder and 5B4B decoder function bypassed

0 = Normal 4B5B and 5B4B operation

BP_SCR

0, RW

Bypass Scrambler/Descrambler Function

1 = Scrambler and descrambler function bypassed

0 = Normal scrambler and descrambler operation

BP_ALIGN

0, RW

Bypass Symbol Alignment Function

1 = Receive functions (descrambler, symbol alignment and symbol

decoding functions) bypassed. Transmit functions (symbol encoder

and scrambler) bypassed

0 = Normal operation

12:11

Reserved

0, RW

Reserved

1, RW

Reserved

9:8

Reserved

0, RW

Reserved

F_LINK_100

0, RW

Force Good Link in 100Mbps:

1 = Force 100Mbps good link status

0 = Normal 100Mbps operation

This bit is useful for diagnostic purposes.

6:5

Reserved

00,RW

Reserved

RPDCTR_EN

1,RW

Reduced Power Down Control Mode:

This bit is used to enable automatic reduced power down

1 = Enable automatic reduced power down

0 = Disable automatic reduced power down

SMRST

0,RC

Reset State Machine:

When writes 1 to this bit, all state machines of PHY will be reset. This bit is

self-clear after reset is completed.

MFPSC

1,RW

MF Preamble Suppression Control:

MII frame preamble suppression control bit

1 = MF preamble suppression bit on

0 = MF preamble suppression bit off

DM9102DEP Datasheet(PDF) 37 Page - Davicom Semiconductor, Inc.

DM9102DEP Datasheet(HTML) 37 Page - Davicom Semiconductor, Inc.

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