DM9102DEP datasheet(22/70 Pages) DAVICOM

22 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

6.2.1 System Control Register (CR0)

Bit

Name

Default

Description

31:24

Reserved

DEH,RO

Reserved

25:22

Reserved

00,RO

Reserved

MRM

0,RW

Memory Read Multiple

When set, the DM9102D will use memory read multiple command (C/BE3~0 1100)

when it initialize the memory read burst transaction as a master device

When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same

master operation

20:1

Reserved

0,RO

Reserved

0,RW

Software Reset

When set, the DM9102D will make a internal reset cycle. All consequent action to

DM9102D2 should wait at least 32 PCI clock cycles for its self-cleared.

6.2.2 Transmit Descriptor Poll Demand (CR1)

31 30

29 28 27 26 25 24 23 22 21 20 19 18

17 16

15 14 13 12 11 10

Bit

Name

Default

Description

31:0

TDP

FFFFFFFFH

,WO

Transmit Descriptor Polling Command

Writing any value to this port will force DM9102D to poll the transmit descriptor. If

the acting descriptor is not available, transmit process will return to suspend state.

If the descriptor shows buffer available, transmit process will begin the data

transfer.

6.2.3 Receive Descriptor Poll Demand (CR2)

31 30

29 28 27 26 25 24 23 22 21 20 19 18

17 16

15 14 13 12 11 10

Bit

Name

Default

Description

31:0

RDP

FFFFFFFFH

,WO

Receive Descriptor Polling Command

Writing any value to this port will force DM9102D to poll the receive descriptor. If

the acting descriptor is not available, receive process will return to suspend state.

If the descriptor shows buffer available, receive process will begin the data transfer.

6.2.4 Receive Descriptor Base Address (CR3)

DM9102DEP Datasheet(PDF) 22 Page - Davicom Semiconductor, Inc.

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