DM9102DEP datasheet(26/70 Pages) DAVICOM

26 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

15:14

TSB

0,RW

Threshold Bits

These bits are set together with CR6 [22] and will decide the exact FIFO threshold

level. The packet transmission will start after the data in the FIFO exceeds the

threshold value.

Bit 22

Bit15

Bit14

Threshold

128 bytes

256 bytes

512 bytes

1024 bytes

64 bytes

128 bytes

192 bytes

256 bytes

TXSC

0,RW

Transmit Start/Stop Command

When set, the transmit process will begin by fetching the transmit descriptor for

available packet data to be transmitted (running state). If the fetched descriptor is

owned by the host, transmit process will enter the suspend state and transmit buffer

unavailable (CR5<2>) is set. Otherwise it will begin to move data from host to

FIFO and transmit out after reaching threshold value.

When reset, the transmit process is placed in the stopped state after completing the

transmission of the current frame.

FCM

0,RW

Force Collision Mode

When set, the transmission process is forced to be the collision status. Meaningful

only in the internal loop-back mode.

11:10

LBM

0,RW

Loop-back Mode

These bits decide two loop-back modes, MAC and PHY, besides normal

operation. These loop-back modes expect transmitted data back to receive path

and ignore collision detection.

Bit11

Bit10

Loop-back Mode

Normal

Internal loop-back

Internal PHY digital loop-back

Internal PHY analog loop-back

FDM

0,RW

Full-duplex Mode

When internal PHY is selected, this bit is the status of full-duplex mode of internal

PHY.

When external PHY is selected, set this bit to make the MAC of the DM9102D

operate in the full-duplex mode.

Reserved

0,RO

Must be Zero

PAM

0,RW

Pass All Multicast

When set, any packet with a multicast destination address is received by the

DM9102D. The packet with a physical address will also be filtered based on the

filter mode setting

0,RW

Promiscuous Mode

When set, any incoming valid frame is received by the DM9102D, and no matter

what the destination address is. The DM9102D is initialized to this mode after reset

operation.

Reserved

0,RO

Must be Zero

DM9102DEP Datasheet(PDF) 26 Page - Davicom Semiconductor, Inc.

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