SC16IS752IPW datasheet(34/59 Pages) NXP

34 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

34 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

9.3 Auto RS-485

EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of

operation, a ‘master’ station transmits an address character followed by data characters

for the addressed ‘slave’ stations. The slave stations examine the received data and

interrupt the controller if the received character is an address character (parity bit = 1).

To use the auto RS-485 RTS mode the software would have to disable the hardware ﬂow

control function.

9.3.1 Normal multidrop mode

The 9-bit mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).

The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an

address byte is received (parity bit = 1). This address byte will cause the UART to set the

parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at

this time), and at the same time puts this address byte in the RX FIFO. After the controller

examines the byte it must make a decision whether or not to enable the receiver; it should

enable the receiver if the address byte addresses its ID address, and must not enable the

receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until

being disabled by the controller after the controller has received a complete message from

the ‘master’ station. If the controller does not disable the receiver after receiving a

message from the ‘master’ station, the receiver will generate a parity error upon receiving

another address byte. The controller then determines if the address byte addresses its ID

address, if it is not, the controller then can disable the receiver. If the address byte

addresses the ‘slave’ ID address, the controller take no further action; the receiver will

receive the subsequent data.

9.3.2 Auto address detection

If Special Character Detect is enabled (EFR[5] is set and XOFF2 contains the address

byte) the receiver will try to detect an address byte that matches the programmed

character in XOFF2. If the received byte is a data byte or an address byte that does not

match the programmed character in XOFF2, the receiver will discard these data. Upon

receiving an address byte that matches the XOFF2 character, the receiver will be

automatically enabled if not already enabled, and the address character is pushed into the

RX FIFO along with the parity bit (in place of the parity error bit). The receiver also

generates a line status interrupt (IER bit 2 must be set to 1 at this time). The receiver will

then receive the subsequent data from the ‘master’ station until being disabled by the

controller after having received a message from the ‘master’ station.

If another address byte is received and this address byte does not match XOFF2

character, the receiver will be automatically disabled and the address byte is ignored. If

the address byte matches XOFF2 character, the receiver will put this byte in the RX FIFO

along with the parity bit in the parity error bit (LSR[2]).

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