ADT7476ARQZ-R7 datasheet(51/67 Pages) ONSEMI

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ADT7476

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Table 19. Fan Tachometer Reading Registers (Power−On Default = 0x00) (Note 1)

R/W

Description

0x28

Read−only

TACH1 low byte.

0x29

Read−only

TACH1 high byte.

0x2A

Read−only

TACH2 low byte.

0x2B

Read−only

TACH2 high byte.

0x2C

Read−only

TACH3 low byte.

0x2D

Read−only

TACH3 high byte.

0x2E

Read−only

TACH4 low byte.

0x2F

Read−only

TACH4 high byte.

1. These registers count the number of 11.11 ms periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH

pulses (default = 2). The number of TACH pulses used to count can be changed using the TACH Pulses per Revolution register (Register 0x7B).

This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes be read, the low byte must

be read first. Both the low and high bytes are then frozen until read. At power−on, these registers contain 0x0000 until the first valid fan TACH

measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF

indicates that a fan is one of the following: stalled or blocked (object jamming the fan), failed (internal circuitry destroyed), or not populated. (The

ADT7476 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should

be set to 0xFFFF.) An alternate function, for example, is TACH4 reconfigured as the THERM pin.

Table 20. Current PWM Duty Cycle Registers (Power−On Default = 0xFF) (Note 1)

R/W

Description

0x30

R/W

PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).

0x31

R/W

PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).

0x32

R/W

PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).

1. These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7476

reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed

control mode. During fan startup, these registers report back 0x00. In manual mode, the PWM duty cycle outputs can be set to any duty cycle

value by writing to these registers.

Table 21.PWM Maximum Duty Cycle (Power−On Default = 0xFF) (Note 1 and 2)

R/W

(Note 2)

Description

0x38

R/W

Maximum duty cycle for PWM1 output, default = 100% (0xFF).

0x39

R/W

Maximum duty cycle for PWM2 output, default = 100% (0xFF).

0x3A

R/W

Maximum duty cycle for PWM3 output, default = 100% (0xFF).

1. These registers set the maximum PWM duty cycle of the PWM output.

2. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

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