ADT7476ARQZ-R7 datasheet(61/67 Pages) ONSEMI

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ADT7476

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Table 42. Register 0x73 — Configuration Register 2 (Power−On Default = 0x00) (Note 1)

Bit No.

Mnemonic

R/W (Note 1)

Description

FanPresDT

R/W

When FanPresenceDT = 1, the state of Bits [3:1] of 0x73 reflects the presence of a 4−wire

fan on the appropriate TACH channel.

Fan1Detect

Read−only

Fan1Detect = 1 indicates that a 4−wire fan is connected to the TACH1 input.

Fan2Detect

Read−only

Fan2Detect = 1 indicates that a 4−wire fan is connected to the TACH2 input.

Fan3Detect

Read−only

Fan3Detect = 1 indicates that a 4−wire fan is connected to the TACH3 input.

AVG

R/W

AVG = 1 indicates that averaging on the temperature and voltage measurements is turned

off. This allows measurements on each channel to be made much faster (x16).

ATTN

R/W

ATTN = 1 indicates that the ADT7476 removes the attenuators from the +2.5 VIN, VCCP,

+5.0 VIN, and +12 VIN inputs. These inputs can be used for other functions such as connecting

up external sensors. It is also possible to remove attenuators from individual channels using

Bits [7:4] of Configuration Register 4 (0x7D).

CONV

R/W

CONV = 1 indicates that the ADT7476 is put into a single−channel ADC conversion mode. In

this mode, the ADT7476 can be made to read continuously from one input only, for example,

Remote 1 temperature. The appropriate ADC channel is selected by writing to Bits [7:5] of

TACH1 minimum high byte register (0x55).

Bits [7:5], Register 0x55

000

001

010

011

100

101

110

111

2.5 V

VCCP

VCC (3.3 V)

5.0 V

12 V

Remote 1 temperature

Local temperature

Remote 2 temperature

Res

This bit is reserved and should not be changed.

1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.

Table 43. Register 0x74 — Interrupt Mask Register 1 (Power−On Default [7:0] = 0x00)

Bit No.

Mnemonic

R/W

Description

[0]

2.5 V/

THERM

R/W

2.5 V/THERM = 1 masks SMBALERT for out−of−limit conditions on the 2.5 V/THERM timer

channel.

[1]

VCCP

R/W

VCCP = 1 masks SMBALERT for out−of−limit conditions on the VCCP channel.

[2]

VCC

R/W

VCC = 1 masks SMBALERT for out−of−limit conditions on the VCC channel.

[3]

5.0 V

R/W

5.0 V = 1 masks SMBALERT for out−of−limit conditions on the 5.0 V channel.

[4]

R1T

R/W

R1T = 1 masks SMBALERT for out−of−limit conditions on the Remote 1 temperature channel.

[5]

R/W

LT = 1 masks SMBALERT for out−of−limit conditions on the local temperature channel.

[6]

R2T

R/W

R2T = 1 masks SMBALERT for out−of−limit conditions on the Remote 2 temperature channel.

[7]

OOL

R/W

OOL = 0 when one or more alerts are generated in Interrupt Status Register 2, assuming all

the mask bits in the Interrupt Mask Register 2 (0x75) =1, SMBALERT is still asserted.

OOL = 1 when one or more alerts are generated in Interrupt Status Register 2, assuming all

the mask bits in the Interrupt Mask Register 2 (0x75) =1, SMBALERT is not asserted.

ADT7476ARQZ-R7 Datasheet(PDF) 61 Page - ON Semiconductor

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