ADT7476ARQZ-R7 datasheet(62/67 Pages) ONSEMI

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ADT7476

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Table 44. Register 0x75 — Interrupt Mask Register 2 (Power−On Default [7:0] = 0x00)

Bit No.

Mnemonic

R/W

Description

[0]

12 V/VC

R/W

When Pin 21 is configured as a 12 V input, 12 V/VC = 1 masks SMBALERT for out−of−limit

conditions on the 12 V channel. When Pin 21 is programmed as VID5, this bit masks an

SMBALERT, if the VID5 VID code bit changes.

[1]

OVT

R/W

OVT = 1 masks SMBALERT for overtemperature THERM conditions.

[2]

FAN1

R/W

FAN1 = 1 masks SMBALERT for a Fan 1 fault.

[3]

FAN2

R/W

FAN2 = 1 masks SMBALERT for a Fan 2 fault.

[4]

FAN3

R/W

FAN3 = 1 masks SMBALERT for a Fan 3 fault.

[5]

F4P

R/W

If Pin 14 is configured as TACH4, F4P = 1 masks SMBALERT for a Fan 4 fault. If Pin 14 is

configured as THERM, F4P = 1 masks SMBALERT for an exceeded THERM timer limit. If Pin 14

is configured as GPIO, F4P = 1 masks SMBALERT when GPIO is an input and GPIO is asserted.

[6]

R/W

D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel.

[7]

R/W

D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel.

Table 45. Register 0x76 — Extended Resolution Register 1 (Power−On Default [7:0] = 0x00) (Note 1)

Bit No.

Mnemonic

R/W

Description

[1:0]

2.5 V

Read−only

2.5 V LSBs. Holds the 2 LSBs of the 10−bit 2.5 V measurement.

[3:2]

VCCP

Read−only

VCCP LSBs. Holds the 2 LSBs of the 10−bit VCCP measurement.

[5:4]

VCC

Read−only

VCC LSBs. Holds the 2 LSBs of the 10−bit VCC measurement.

[7:6]

5.0 V

Read−only

5.0 V LSBs. Holds the 2 LSBs of the 10−bit 5.0 V measurement.

1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

Table 46. Register 0x77 — Extended Resolution Register 2 (Power−On Default [7:0] = 0x00) (Note 1)

Bit No.

Mnemonic

R/W

Description

[1:0]

12 V

Read−only

12 V LSBs. Holds the 2 LSBs of the 10−bit 12 V measurement.

[3:2]

TDM1

Read−only

Remote 1 temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 1 temperature

measurement.

[5:4]

LTMP

Read−only

Local temperature LSBs. Holds the 2 LSBs of the 10−bit local temperature measurement.

[7:6]

TDM2

Read−only

Remote 2 temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 2 temperature

measurement.

1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

ADT7476ARQZ-R7 Datasheet(PDF) 62 Page - ON Semiconductor

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