ADT7476ARQZ-R7 datasheet(22/67 Pages) ONSEMI

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ADT7476

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Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum

speed. Alternatively, indicates that the THERM limit has

been exceeded, if the THERM function is used.

Alternatively, indicates the status of GPIO6.

Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below

minimum speed.

Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum

speed.

Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum

speed.

Bit 1 (OVT) = 1, indicates a THERM overtemperature limit

has been exceeded.

Bit 0 (12 V/VC) = 1, indicates a 12 V high or low limit has

been exceeded. If the VID code change function is used, this

bit indicates a change in VID code on the VID0 to VID4

inputs.

SMBALERT Interrupt Behavior

The ADT7476 can be polled for status, or an SMBALERT

interrupt can be generated for out−of−limit conditions. It is

important to note how the SMBALERT output and status

bits behave when writing interrupt handler software.

Figure 29. SMBALERT and Status Bit Behavior

STICKY

STATUS BIT

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

SMBALERT

Figure 29 shows how the SMBALERT output and sticky

status bits behave. Once a limit is exceeded, the

corresponding status bit is set to 1. The status bit remains set

until the error condition subsides and the status register is

read. The status bits are referred to as sticky because they

remain set until read by software. This ensures that an

out−of−limit event cannot be missed if the software is

periodically polling the device.

Note that:

• The SMBALERT output remains low for the entire

duration that a reading is out−of−limit and until the

status register has been read. This has implications on

how software handles the interrupt.

• THERM overtemperature events are not sticky. They

reset immediately after the overtemperature condition

ceases.

Handling SMBALERT Interrupts

To prevent the system from being tied up servicing

interrupts, it is recommend to handle the SMBALERT

interrupt as follows:

1. Detect the SMBALERT assertion.

2. Enter the interrupt handler.

3. Read the status registers to identify the interrupt

source.

4. Mask the interrupt source by setting the

appropriate mask bit in the interrupt mask registers

(0x74 and 0x75).

5. Take the appropriate action for a given interrupt

source.

6. Exit the interrupt handler.

7. Periodically poll the status registers. If the

interrupt status bit has cleared, reset the

corresponding interrupt mask bit to 0. This causes

the SMBALERT output and status bits to behave

as shown in Figure 30.

Masking Interrupt Sources

Interrupt Mask Register 1 (0x74) and Interrupt Mask

masked to prevent SMBALERT interrupts. Note: Masking

an interrupt source prevents only the SMBALERT output

from being asserted; the appropriate status bit is set

normally.

Figure 30. How Masking the Interrupt Source Affects

SMBALERT Output

STICKY

STATUS BIT

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

INTERRUPT

MASK BIT SET

SMBALERT

INTERRUPT MASK BIT

CLEARED

(SMBALERT REARMED)

Interrupt Mask Register 1 (0x74)

Bit 7 (OOL) = 1, masks SMBALERT for any alert condition

flagged in Interrupt Status Register 2.

Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.

Bit 5 (LT) = 1, masks SMBALERT for local temperature.

Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.

Bit 3 (5.0 V) = 1, masks SMBALERT for 5.0 V channel.

Bit 2 (VCC) = 1, masks SMBALERT for VCC channel.

Bit 1 (VCCP) = 1, masks SMBALERT for VCCP channel.

Bit 0 (2.5 V) = 1, masks SMBALERT for 2.5 VIN/ THERM.

ADT7476ARQZ-R7 Datasheet(PDF) 22 Page - ON Semiconductor

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