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56F8014 Datasheet(PDF) 59 Page - Freescale Semiconductor, Inc |
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56F8014 Datasheet(HTML) 59 Page - Freescale Semiconductor, Inc |
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59 / 124 page ![]() Register Descriptions 56F8014 Technical Data, Rev. 11 Freescale Semiconductor 59 • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.5.13.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.5.14 IRQ Pending Register 1 (IRQP1) Figure 5-16 IRQ Pending Register 1 (IRQP1) 5.5.14.1 IRQ Pending (PENDING)—Bits 32–17 This register combines with IRQP0 and IRQP2 to represent the pending IRQs for interrupt vector numbers 2 through 45. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.5.15 IRQ Pending Register 2 (IRQP2) Figure 5-17 IRQ Pending Register 2 (IRQP2) 5.5.15.1 IRQ Pending (PENDING)—Bits 45–33 This register combines with IRQP0 and IRQP1 to represent the pending IRQs for interrupt vector numbers 2 through 45. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.5.16 Interrupt Control Register (ICTRL) Figure 5-18 Interrupt Control Register (ICTRL) Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING[32:17] Write RESET 11111 1111111 1111 Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 1 1 1 PENDING[45:33] Write RESET 11111 1111111 1111 $Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read INT IPIC VAB INT_ DIS 1 1 1 0 0 Write RESET 00000 0000001 1100 |
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