56F8014 datasheet(79/124 Pages) FREESCALE

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Resets

56F8014 Technical Data, Rev. 11

Freescale Semiconductor

be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator.

All peripherals, except the COP/watchdog timer, run at the system clock (peripheral bus) frequency1,

which is the same as the main processor frequency in this architecture. The COP timer runs at

MSTR_OSC / 1024. The maximum frequency of operation is SYS_CLK = 32MHz. The only exception is

the Quad Timer and PWM, which can be configured to operate at three times the system bus rate using

TCR and PCR controls, provided the PLL is active and selected.

6.6 Resets

The SIM supports four sources of reset, as shown in Figure 6-15. The two asynchronous sources are the

external reset pin and the Power-On Reset (POR). The two synchronous sources are the software reset,

which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1, and the COP

reset. The SIM uses these to generate resets for the internal logic. These are outlined in Table 6-4. The

first column lists the four primary resets which are calculated. The JTAG circuitry is reset by the Power-On

Reset. Columns two through five indicate which reset sources trigger these reset signals. The last column

provides additional detail.

Figure 6-15 provides a graphic illustration of the details in Table 6-4. Note that the POR_Delay blocks

use the Relaxation Oscillator Clock as their time base since other system clocks are inactive during this

phase of reset.

1. The Quad Timer and PWM modules can be operated at three times the IPBus clock frequency.

Table 6-4 Primary System Resets

Reset Sources

Reset Signal

POR

External

Software

COP

Comments

EXTENDED_POR

Stretched version of POR. Relevant 64

Relaxation Oscillator Clock cycles after

POR deasserts.

CLKGEN_RST

Released 32 Relaxation Oscillator Clock

cycles after all reset sources have

released.

PERIP_RST

Releases 32 Relaxation Oscillator Clock

cycles after the CLKGEN_RST is

released.

CORE_RST

Releases 32 SYS_CLK periods after

PERIP_RST is released.

56F8014 Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

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