EL5420CSZ datasheet(13/20 Pages) INTERSIL

13 / 20 page

FN7186.6

March 4, 2009

supply voltage, plus the power in the IC due to the loads as

shown in Equation 2:

when sourcing, and:

when sinking.

where:

• i = 1 to 2 for dual and 1 to 4 for quad

•VS = Total supply voltage

•ISMAX = Maximum supply current per amplifier

•VOUTi = Maximum output voltage of the application

•ILOADi = Load current

If we set the two PDMAX equations equal to each other, we

can solve for RLOADi to avoid device overheat. Figure 27

provide a convenient way to see if the device will overheat.

The maximum safe power dissipation can be found

graphically, based on the package type and the ambient

temperature. By using the previous equation, it is a simple

matter to see if PDMAX exceeds the device's power derating

curves. To ensure proper operation, it is important to observe

the recommended derating curves in Figure 27.

Unused Amplifiers

It is recommended that any unused amplifiers in a dual and

a quad package be configured as a unity gain follower. The

inverting input should be directly connected to the output

and the non-inverting input tied to the ground plane.

Driving Capacitive Loads

The EL5120, EL5220, and EL5420 can drive a wide range of

capacitive loads. As load capacitance increases, however,

the -3dB bandwidth of the device will decrease and the

peaking will increase. The amplifiers drive 10pF loads in

parallel with 10k

Ω with just 1.5dB of peaking, and 100pF

with 6.4dB of peaking. If less peaking is desired in these

applications, a small series resistor (usually between 5

Ω and

Ω) can be placed in series with the output. However, this

will obviously reduce the gain slightly. Another method of

reducing peaking is to add a “snubber” circuit at the output.

A snubber is a shunt load consisting of a resistor in series

with a capacitor. Values of 150

Ω and 10nF are typical. The

advantage of a snubber is that it does not draw any DC load

current or reduce the gain

Power Supply Bypassing and Printed Circuit

Board Layout

The EL5120, EL5220, and EL5420 can provide gain at high

frequency. As with any high-frequency device, good printed

circuit board layout is necessary for optimum performance.

Ground plane construction is highly recommended, lead

lengths should be as short as possible and the power supply

pins must be well bypassed to reduce the risk of oscillation.

For normal single supply operation, where the VS- pin is

connected to ground, a 0.1µF ceramic capacitor should be

placed from VS+ to pin to VS- pin. A 4.7µF tantalum

capacitor should then be connected in parallel, placed in the

region of the amplifier. One 4.7µF capacitor may be used for

multiple devices. This same capacitor combination should be

placed at each supply pin to ground if split supplies are to be

used.

DMAX

ΣiV

SMAX

S+

(

OUT i )

LOAD i

–

[]

(EQ. 2)

DMAX

ΣiV

SMAX

OUTi

(

S- )

LOADi

–

[]

(EQ. 3)

3.0

2.5

2.0

1.5

1.0

0.5

255075

100

150

AMBIENT TEMPERATURE (°C)

2.27W

θJA = 44°C/W

QFN16

125

1.22W

870mW

θJA = 115°C/W

MSOP8

θJA = 93°C/W

TSSOP14

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.08W

θJA = 82°C/W

SOIC14

1.800W

θJA = 55°C/W

DFN8

FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

EL5120, EL5220, EL5420

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