MSC8102 datasheet(34/80 Pages) FREESCALE

34 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

2-4

Freescale Semiconductor

Specifications

2.5 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and

inputs. When designing systems such as DSP farms using the DSI, use a device loading of 4 pF per pin. AC timings

are based on a 50 pF load, except where noted otherwise, and a 50

Ω transmission line. For any additional pF, add

0.07 ns for the delay and take the RC delay into consideration.

2.5.1

Output Buffer Impedances

2.5.2

Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power.

Section 2.5.3 describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics.

You must use the following guidelines when starting up an MSC8102 device:

•

PORESET

and TRST must be asserted externally for the duration of the power-up sequence. See Table 2-10

for timing.

•

If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up

the VDDH levels and then the VDD levels (see Figure 2-3 and Figure 2-4).

•

CLKIN

can start toggling after VDDH reaches its nominal level, but it must toggle before VDD reaches 0.5 V to

guarantee correct device operation (see Figure 2-2 and Figure 2-4).

The following figures show acceptable start-up sequence examples. Figure 2-2 shows a sequence in which VDD and

VDDH are raised together. Figure 2-3 shows a sequence in which CLKIN starts toggling after VDDH reaches its

nominal level and before VDD is applied. Figure 2-4 shows a sequence in which VDD is raised after VDDH and CLKIN

begins to toggle shortly before VDD reaches the 0.5 V level.

Figure 2-1.

Overshoot/Undershoot Voltage for VIH and VIL

Table 2-5.

Output Buffer Impedances

Output Buffers

Typical Impedance (

Ω)

System bus

Memory controller

Parallel I/O

Note:

These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.

GND

GND – 0.3 V

GND – 0.7 V

VIL

VIH

Must not exceed 10% of clock period

VDDH + 20%

VDDH + 10%

VDDH

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