MSC8102 datasheet(41/80 Pages) FREESCALE

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AC Timings

MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

2-11

Table 2-13.

AC Timing for SIU Outputs

No.

Characteristic

Value1

Units

30 pF

50 pF

Min delay from the 50% level of the REFCLK for all signals

1.0

PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge

•

Pipeline mode

•

Non-pipeline mode

6.0

6.5

7.5

8.0

32a

Address bus max delay from the 50% level of the REFCLK rising edge

•

Multi-master mode (SIUBCR[EBM] = 1)

•

Single-master mode (SIUBCR[EBM] = 0)

7.2

4.1

8.7

5.6

32b

Address attributes: TT/TC/TBST/TSIZ/GBL max delay from the 50% level of the REFCLK

rising edge

5.8

7.3

32c

BADDR max delay from the 50% level of the REFCLK rising edge

4.8

6.3

33a

Data bus max delay from the 50% level of the REFCLK rising edge

•

Pipeline mode

•

Non-pipeline mode

5.0

7.5

6.5

9.0

33b

DP max delay from the 50% level of the REFCLK rising edge

•

Pipeline mode

•

Non-pipeline mode

5.5

7.5

7.0

9.0

Memory controller signals/ALE max delay from the 50% level of the REFCLK rising edge

5.9

7.4

35a

DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising edge

5.5

7.0

35b

AACK/ABB/TS/CS max delay from the 50% level of the REFCLK rising edge

6.3

7.8

Notes:

Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level.

The maximum bus frequency depends on the mode:

• In 60x-compatible mode connected to another MSC8102 device, the frequency is determined by adding the input and output

longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance.

• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8102.

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