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FX980 Datasheet(PDF) 33 Page - CML Microcircuits |
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FX980 Datasheet(HTML) 33 Page - CML Microcircuits |
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33 / 86 page ![]() TETRA Baseband Processor FX980 © 1997 Consumer Microcircuits Limited 33 D/980/3 AuxAdcData Title: Auxiliary ADC Data registers Address: (Eight registers) $0x10 to $0x17 Function: R Description: These registers enable the user to inspect the conversion value for each of the four auxiliary ADCs. There are two read registers per ADC, one to obtain the least significant two bits of the data, the other for the most significant eight bits. Reading these registers does not affect the ADC conversion cycle. Reading the MSB read register directly reads the ADC output and simultaneously causes the two bits in the LSB read register to be written into a holding register. This holding register is read when the LSB read register is read. This mechanism is necessary to allow the user to read MSB and LSB data from the same ADC conversion cycle. If only the MSB read register is read, the converter can be considered as an 8-bit ADC. If a 10-bit conversion is required, the MSB read register must be read first. Bit Name Active State Function Address $0x10 7:0 Adc1MsbData Data R Most significant eight bits of the data from the last conversion of AuxAdc1. Address $0x11 7:2 R Reserved. Bit values are not defined. 1:0 Adc1LsbData Data R Least significant two bits of the data from the last conversion of AuxAdc1. Address $0x12 7:0 Adc2MsbData Data R Most significant eight bits of the data from the last conversion of AuxAdc2. Address $0x13 7:2 R Reserved. Bit values are not defined. 1:0 Adc2LsbData Data R Least significant two bits of the data from the last conversion of AuxAdc2. Address $0x14 7:0 Adc3MsbData Data R Most significant eight bits of the data from the last conversion of AuxAdc3. Address $0x15 7:2 R Reserved. Bit values are not defined. 1:0 Adc3LsbData Data R Least significant two bits of the data from the last conversion of AuxAdc3. Address $0x16 7:0 Adc4MsbData Data R Most significant eight bits of the data from the last conversion of AuxAdc4. Address $0x17 7:2 R Reserved. Bit values are not defined. 1:0 Adc4LsbData Data R Least significant two bits of the data from the last conversion of AuxAdc4. |
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