CY8C52 datasheet(5/94 Pages) CYPRESS

5 / 94 page

PRELIMINARY

PSoC® 5: CY8C52 Family Datasheet

Document Number: 001-66236 Rev. **

Page 5 of 94

PSoC uses a JTAG (4 wire) or SWD (2 wire) interface for

programming, debug, and test. Using these standard interfaces

enables the designer to debug or program the PSoC with a

variety of hardware solutions from Cypress or third party

vendors. The Cortex-M3 debug and trace modules include FPB,

DWT, ETM, and ITM. These modules have many features to help

solve difficult debug and trace problems. Details of the

programming, test, and debugging interfaces are discussed in

the “Programming, Debug Interfaces, Resources” section on

page 49 of this data sheet.

2. Pinouts

The Vddio pin that supplies a particular set of pins is indicated

by the black lines drawn on the pinout diagrams in Figure 2-1 and

Figure 2-2. Using the Vddio pins, a single PSoC can support

multiple interface voltage levels, eliminating the need for off-chip

level shifters. Each Vddio may sink up to 100 mA total to its

associated I/O pins. On the 68-pin and 100-pin devices each set

of Vddio associated pins may sink up to 100 mA. The 48 pin

device may sink up to 100 mA total for all Vddio0 plus Vddio2

associated I/O pins and 100 mA total for all Vddio1 plus Vddio3

associated I/O pins.

Figure 2-1. 68-pin QFN Part Pinout[3]

(TRACEDATA[2], GPIO) P2[6]

(TRACEDATA[3], GPIO) P2[7]

(SIO) P12[4]

(SIO) P12[5]

Vssb

Ind

Vboost

Vbat

Vssd

XRES

(TMS, SWDIO) P1[0]

(TCK, SWDCK) P1[1]

(GPIO) P1[2]

(TDO, GPIO) P1[3]

(TDI, GPIO) P1[4]

(GPIO) P1[5]

Vddio1

P0[3] (GPIO, OpAmp0-/Extref0)

P0[2] (GPIO, OpAmp0+)

P0[1] (GPIO, OpAmp0out)

P0[0] (GPIO, OpAmp2out)

P12[3] (SIO)

P12[2] (SIO)

Vssd

Vdda

Vssa

Vcca

P15[3] (GPIO, kHz XTAL: Xi)

P15[2] (GPIO, kHz XTAL: Xo)

P12[1] (SIO)

P12[0] (SIO)

P3[7] (GPIO, OpAmp3out)

P3[6] (GPIO, OpAmp1out)

Vddio3

QFN

(Top View)

Lines show Vddio

to I/O supply

association

Notes

3. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

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