CY8C52 datasheet(11/94 Pages) CYPRESS

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PSoC® 5: CY8C52 Family Datasheet

Document Number: 001-66236 Rev. **

Page 11 of 94

4.2 Cache Controller

The CY8C52 family has a 1 KB cache between the CPU and the

flash memory. This improves instruction execution rate and

reduces system power consumption by requiring less frequent

flash access.

4.3 DMA and PHUB

The PHUB and the DMA controller are responsible for data

transfer between the CPU and peripherals, and also data

transfers between peripherals. The PHUB and DMA also control

device configuration during boot. The PHUB consists of:

A central hub that includes the DMA controller, arbiter, and

router

Multiple spokes that radiate outward from the hub to most

peripherals

There are two PHUB masters: the CPU and the DMA controller.

Both masters may initiate transactions on the bus. The DMA

channels can handle peripheral communication without CPU

intervention. The arbiter in the central hub determines which

DMA channel is the highest priority if there are multiple requests.

4.3.1 PHUB Features

CPU and DMA controller are both bus masters to the PHUB

Eight multi-layer AHB bus parallel access paths (spokes) for

peripheral access

Simultaneous CPU and DMA access to peripherals located on

different spokes

Simultaneous DMA source and destination burst transactions

on different spokes

Supports 8-, 16-, 24-, and 32-bit addressing and data

4.3.2 DMA Features

24 DMA channels

Each channel has one or more transaction descriptors (TDs)

to configure channel behavior. Up to 127 total TDs can be

defined

TDs can be dynamically updated

Eight levels of priority per channel

Any digitally routable signal, the CPU, or another DMA channel,

can trigger a transaction

Each channel can generate up to two interrupts per transfer

Transactions can be stalled or canceled

Supports transaction size of infinite or 1 to 64 k bytes

Large transactions may be broken into smaller bursts of 1 to

127 bytes

TDs may be nested and/or chained for complex transactions

CONTROL

A 2-bit register for controlling the operating

mode.

Bit 0: 0 = privileged level in thread mode,

1 = user level in thread mode.

Bit 1: 0 = default stack (MSP) is used,

1 = alternate stack is used. If in thread mode or

user level then the alternate stack is the PSP.

There is no alternate stack for handler mode; the

bit must be 0 while in handler mode.

Table 4-2. Cortex M3 CPU Registers (continued)

Description

Table 4-3. PHUB Spokes and Peripherals

PHUB Spokes

Peripherals

SRAM

IOs, PICU

PHUB local configuration, Power manager,

Clocks, IC, EEPROM, Flash programming

interface

Analog interface and trim, Decimator

USB, CAN, I2C, Timers, Counters, and PWMs

Reserved

UDBs group 1

UDBs group 2

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