CY8C52 datasheet(24/94 Pages) CYPRESS

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PSoC® 5: CY8C52 Family Datasheet

Document Number: 001-66236 Rev. **

Page 24 of 94

The boost converter can be operated in two different modes:

active and standby. Active mode is the normal mode of operation

where the boost regulator actively generates a regulated output

voltage. In standby mode, most boost functions are disabled,

thus reducing power consumption of the boost circuit. The

converter can be configured to provide low power, low current

regulation in the standby mode. The external 32 kHz crystal can

be used to generate inductor boost pulses on the rising and

falling edge of the clock when the output voltage is less than the

programmed value. This is called automatic thump mode (ATM).

The boost typically draws 200 µA in active mode and 12 µA in

standby mode. The boost operating modes must be used in

conjunction with chip power modes to minimize the total chip

power consumption. Table 6-4 lists the boost power modes

available in different chip power modes.

If the boost converter is not used in a given application, tie the

VBAT, VSSB, and VBOOST pins to ground and leave the Ind pin

unconnected.

6.3 Reset

CY8C52 has multiple internal and external reset sources

available. The reset sources are:

Power source monitoring: The analog and digital power

voltages, VDDA, VDDD, VCCA, and VCCD are monitored in

several different modes during power up, active mode, and

sleep mode (buzzing). If any of the voltages goes outside

predetermined ranges then a reset is generated. The monitors

are programmable to generate an interrupt to the processor

under certain conditions before reaching the reset thresholds.

External: The device can be reset from an external source by

pulling the reset pin (XRES) low. The XRES pin includes an

internal pull up to VDDIO1. VDDD, VDDA, and VDDIO1 must all

have voltage applied before the part comes out of reset.

Watchdog timer: A watchdog timer monitors the execution of

instructions by the processor. If the watchdog timer is not reset

by firmware within a certain period of time, the watchdog timer

generates a reset.

Software: The device can be reset under program control.

Figure 6-7. Resets

The term system reset indicates that the processor as well as

analog and digital peripherals and registers are reset.

A reset status register holds the source of the most recent reset

or power voltage monitoring interrupt. The program may

examine this register to detect and report exception conditions.

This register is cleared after a power on reset.

6.3.1 Reset Sources

6.3.1.1 Power Voltage Level Monitors

IPOR - Initial Power on Reset

At initial power on, IPOR monitors the power voltages VDDD

and VDDA, both directly at the pins and at the outputs of the

corresponding internal regulators. The trip level is not precise.

It is set to approximately 1 volt, which is below the lowest

specified operating voltage but high enough for the internal

circuits to be reset and to hold their reset state. The monitor

generates a reset pulse that is at least 100 ns wide. It may be

much wider if one or more of the voltages ramps up slowly.

To save power the IPOR circuit is disabled when the internal

digital supply is stable. Voltage supervision is then handed off

to the precise low voltage reset (PRES) circuit. When the

voltage is high enough for PRES to release, the IMO starts.

PRES - Precise Low Voltage Reset

This circuit monitors the outputs of the analog and digital

internal regulators after power up. The regulator outputs are

compared to a precise reference voltage. The response to a

PRES trip is identical to an IPOR reset.

In normal operating mode, the program cannot disable the

digital PRES circuit. The analog regulator can be disabled,

which also disables the analog portion of the PRES. The PRES

circuit is disabled automatically during sleep and hibernate

modes, with one exception: During sleep mode the regulators

are periodically activated (buzzed) to provide supervisory

services and to reduce wakeup time. At these times the PRES

circuit is also buzzed to allow periodic voltage monitoring.

Table 6-4. Chip and Boost Power Modes Compatibility

Chip Power Modes

Boost Power Modes

Chip-active mode

Boost can be operated in either active

or standby mode.

Chip-sleep mode

Boost can be operated in either active

or standby mode. However, it is recom-

mended to operate boost in standby

mode for low power consumption

Chip-hibernate mode

Boost can only be operated in active

mode. However, it is recommended not

to use boost in chip hibernate mode

due to high current consumption in

boost active mode

Reset

Controller

Watchdog

Timer

External

Reset

Power

Voltage

Level

Monitors

Software

Reset

Vddd Vdda

Reset

System

Reset

Processor

Interrupt

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