CYUSB3014 datasheet(6/38 Pages) CYPRESS

6 / 38 page

PRELIMINARY

CYUSB3014

Document Number 001-52136 Rev. *H

Page 6 of 38

Figure 5. Carkit UART Pass Through Block Diagram

GPIF II

EZ-USB FX3 offers a high performance General Programmable

Interface, GPIF II. This interface enables functionality similar to

but more advanced than FX2LP's GPIF and Slave FIFO

interfaces.

The GPIF II is a programmable state machine that enables a

flexible interface that may function either as a master or slave in

industry standard or proprietary interfaces. Both parallel and

serial interfaces may be implemented with GPIF II.

The features of the GPIF II are summarized as follows:

■ Functions as master or slave

■ Provides 256 firmware programmable states

■ Supports 8 bit, 16 bit and 32 bit parallel data bus

■ Enables interface frequencies up to 100 MHz.

■ Supports 14 configurable control pins when 32 bit data bus is

used. All control pins can be either input/output or bidirectional.

■ Supports 16 configurable control pins when 16/8 data bus is

used. All control pins can be either input/output or bidirectional.

GPIFII state transitions occur based on control input signals. The

control output signals are driven as a result of GPIFII state transi-

tions. The behavior of the GPIFII state machine is defined by a

GPIFII descriptor. The GPIFII descriptor is designed such that

the required interface specifications are met. 8kB of memory

(separate from the 512kB of embedded SRAM) is dedicated as

GPIF II Waveform memory where the GPIF II descriptor is stored

in a specific format.

Cypress’ GPIFII Designer Tool enables fast development of

GPIFII descriptors and includes examples for common inter-

faces.

Example implementations of GPIF II are the Asynchronous

Slave FIFO and Synchronous Slave FIFO interfaces.

Slave FIFO interface

The Slave FIFO interface signals are shown in Figure 6. This

interface allows an external processor to directly access upto 4

buffers internal to EZ-USB FX3. Further details of the Slave FIFO

interface are described on page 19

Note: Access to all 32 buffer is also supported over Slave FIFO

interface. For details, please contact Cypress Applications

Support.

Figure 6. Slave FIFO Interface

CPU

EZ-USB FX3 has an on chip 32-bit, 200 MHz ARM926EJ-S core

CPU. The core has direct access to 16kB of Instruction Tightly

Coupled Memory (TCM) and 8kB of Data TCM. The

ARM926EJ-S core provides a JTAG interface for firmware

debugging.

EZ-USB FX3 also integrates 512 kB of embedded SRAM for

code and data, and 8kB of Instruction cache and Data cache.

EZ-USB FX3 implements highly efficient and flexible DMA

connectivity between the various peripherals (i.e. USB, GPIF II,

I2S, SPI,UART), requiring firmware to only configure data

accesses between peripherals which are then managed by the

DMA fabric.

EZ-USB FX3 allows for easy application development on

industry standard development tools for ARM926EJ-S.

Examples of EZ-USB FX3 firmware are available with the

Cypress EZ-USB FX3 Development Kit.

Software APIs that can be ported to an external processor are

available with the Cypress EZ-USB FX3 Software Development

Kit.

Carkit UART Pass Through

Carkit UART pass through

interface on GPIF(TM)II

interface.

RXD (DP)

TXD (DM)

USB PHY

TXD

RXD

UART_TXD

UART_RXD

GPIO[48]

(UART_TX)

GPIO[49]

(UART_RX)

Carkit UART pass through

interface on GPIOs

External

Processor

EZ-USB FX3

SLCS#

A[1:0]

D[31:0]

SLRD#

SLOE#

SLWR#

PKTEND

FLAGA

FLAGB

Note: Multiple Flags may be configured.

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