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CYUSB3014 Datasheet(PDF) 28 Page - Cypress Semiconductor |
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CYUSB3014 Datasheet(HTML) 28 Page - Cypress Semiconductor |
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28 / 38 page ![]() PRELIMINARY CYUSB3014 Document Number 001-52136 Rev. *H Page 28 of 38 I2S Timing Diagram Figure 15. I2S Transmit Cycle Note 8. All parameters guaranteed by design and validated through characterization. Table 13. I2S Timing Parameters[8] Parameter Description Min Max Units tT I2S transmitter clock cycle Ttr – ns tTL I2S transmitter cycle LOW period 0.35 Ttr – ns tTH I2S transmitter cycle HIGH period 0.35 Ttr – ns tTR I2S transmitter rise time – 0.15 Ttr ns tTF I2S transmitter fall time – 0.15 Ttr ns tThd I2S transmitter data hold time 0 – ns tTd I2S transmitter delay time – 0.3tT ns Note tT is selectable through clock gears. Max Ttr is designed for 96 kHz codec at 32 bits to be 326 ns (3.072 MHz). [+] Feedback [+] Feedback |
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