CYUSB3014 datasheet(8/38 Pages) CYPRESS

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PRELIMINARY

CYUSB3014

Document Number 001-52136 Rev. *H

Page 8 of 38

Reset

Hard Reset

A hard reset is initiated by asserting the Reset# pin on EZ-USB

FX3. The specific reset sequence and timing requirements are

detailed in Figure 17 and Table 15.

Soft Reset

Soft Reset involves the processor setting the appropriate bits in

the PP_INIT control register. There are two types of Soft Reset:

■ CPU Reset - The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Whole Device Reset - This reset is identical to Hard Reset. The

firmware must be reloaded following a Whole Device Reset.

Clocking

EZ-USB FX3 allows either a crystal to be connected between the

XTALIN and XTALOUT pins or an external clock to be connected

at the CLKIN pin.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

EZ-USB FX3 has an on-chip oscillator circuit that uses an

external 19.2 MHz (±100 ppm) crystal (when the crystal option is

used). The FSLC[2:0] pins must be configured appropriately to

select the crystal option/clock frequency option. The configu-

ration options are shown in Table 3.

Clock inputs to EZ-USB FX3 must meet the phase noise and

jitter requirements specified in Table 4.

The input clock frequency is independent of the clock/data rate

of EZ-USB FX3 core or any of the device interfaces (including

P-Port and S-Port). The internal PLL applies the appropriate

clock multiply option depending on the input frequency.

32-kHz Watchdog Timer Clock Input

EZ-USB FX3 includes a watchdog timer. The watchdog timer can

be used to interrupt the ARM926EJ-S core, auto wakeup

EZ-USB FX3 in Standby mode and reset the ARM926EJ-S core.

The watch dog timer runs off a 32 kHz clock. This 32 kHz clock

may optionally be supplied from an external source on a

dedicated pin of EZ-USB FX3.

The watchdog timer can be disabled by firmware.

Requirements for the optional 32 kHZ clock input are listed in

Table 5.

Table 3. Crystal/Clock Frequency Selection

FSLC[2]

FSLC[1]

FSLC[0]

Crystal/ Clock Frequency

19.2 MHz crystal

19.2 MHz input CLK

26 MHz input CLK

38.4 MHz input CLK

52 MHz input CLK

Table 4. Input Clock Specifications for EZ-USB FX3

Parameter

Description

Specification

Units

Min

Max

Phase noise

100 Hz Offset

–

–75

1 kHz Offset

–

–104

10 kHz Offset

–

–120

100 kHz Offset

–

–128

1 MHz Offset

–

–130

Maximum frequency deviation

–

150

ppm

Duty cycle

Overshoot

–

Undershoot

–

–3

Rise time/fall time

–

Table 5. 32 kHz Clock Input Requirements

Parameter

Min

Max

Units

Duty cycle

Frequency deviation

–

±200

ppm

Rise time/fall time

–

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