LPC1850 datasheet(68/157 Pages) PHILIPS

68 / 157 page

LPC1850_30_20_10

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Preliminary data sheet

Rev. 3 — 6 December 2011

68 of 157

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

7.3 AHB multilayer matrix

7.4 Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

7.4.1 Features

• Controls system exceptions and peripheral interrupts.

• In the LPC1850/30/20/10, the NVIC supports 32 vectored interrupts.

• 8 programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table.

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

(1) Not available on all parts (see Table 2).

Fig 8.

AHB multilayer matrix master and slave connections

ARM

CORTEX-M3

TEST/DEBUG

INTERFACE

GPDMA

ETHERNET(1)

USB1(1)

USB0(1)

LCD(1)

SD/

MMC

EXTERNAL

MEMORY

CONTROLLER

AHB REGISTER

INTERFACES,

APB, RTC DOMAIN

PERIPHERALS

32 kB AHB SRAM

16 kB AHB SRAM(1)

16 kB AHB SRAM

slaves

64 kB ROM

64/96 kB LOCAL SRAM

40 kB LOCAL SRAM

System

bus

I-code

bus

D-code

bus

masters

SPIFI

AHB MULTILAYER MATRIX

= master-slave connection

002aag550

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