LPC1850 datasheet(83/157 Pages) PHILIPS

83 / 157 page

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Preliminary data sheet

Rev. 3 — 6 December 2011

83 of 157

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

7.14.6 C_CAN

Remark: The LPC1850/30/20/10 contain two C_CAN controllers.

Controller Area Network (CAN) is the definition of a high performance communication

protocol for serial data communication. The C_CAN controller is designed to provide a full

implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a very high level of reliability.

7.14.6.1

Features

• Conforms to protocol version 2.0 parts A and B.

• Supports bit rate of up to 1 Mbit/s.

• Supports 32 Message Objects.

• Each Message Object has its own identifier mask.

• Provides programmable FIFO mode (concatenation of Message Objects).

• Provides maskable interrupts.

• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

• Provides programmable loop-back mode for self-test operation.

7.15 Counter/timers and motor control

7.15.1 General purpose 32-bit timers/external event counter

Remark: The LPC1850/30/20/10 include four 32-bit timer/counters.

The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA

requests, or perform other actions at specified timer values, based on four match

registers. Each timer/counter also includes two capture inputs to trap the timer value when

an input signal transitions, optionally generating an interrupt.

7.15.1.1

Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

LPC1850 Datasheet(PDF) 83 Page - NXP Semiconductors

LPC1850 Datasheet(HTML) 83 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL