LPC1850 datasheet(79/157 Pages) PHILIPS

79 / 157 page

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Preliminary data sheet

Rev. 3 — 6 December 2011

79 of 157

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

The LCD controller provides all of the necessary control signals to interface directly to a

variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT

panels can be operated. The display resolution is selectable and can be up to 1024

 768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.

An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the

displayed data) while still supporting a large number of colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other system functions. A built-in FIFO acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time needed to operate the display.

7.13.8.1

Features

• AHB master interface to access frame buffer.

• Setup and control via a separate AHB slave interface.

• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.

• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

• Supports single and dual-panel color STN displays.

• Supports Thin Film Transistor (TFT) color displays.

• Programmable display resolution including, but not limited to: 320  200, 320  240,

640

 200, 640  240, 640  480, 800  600, and 1024  768.

• Hardware cursor support for single-panel displays.

• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

• 16 bpp true-color non-palettized for color STN and TFT.

• 24 bpp true-color non-palettized for color TFT.

• Programmable timing for different display panels.

• 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM.

• Frame, line, and pixel clock signals.

• AC bias signal for STN, data enable signal for TFT panels.

• Supports little and big-endian, and Windows CE data formats.

• LCD panel clock may be generated from the peripheral clock, or from a clock input

pin.

7.13.9 Ethernet

Remark: Ethernet is available on parts LPC1850/30 (see Table 2).

7.13.9.1

Features

• 10/100 Mbit/s

• TCP/IP hardware checksum

• IP checksum

• DMA support

LPC1850 Datasheet(PDF) 79 Page - NXP Semiconductors

LPC1850 Datasheet(HTML) 79 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL