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LPC1850 Datasheet(PDF) 89 Page - NXP Semiconductors |
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LPC1850 Datasheet(HTML) 89 Page - NXP Semiconductors |
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89 / 157 page ![]() LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 3 — 6 December 2011 89 of 157 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller The LPC1850/30/20/10 support four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. The LPC1850/30/20/10 can wake up from Deep-sleep, Power-down, and Deep power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in the RTC power domain. 7.19 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. Fig 11. LPC1850/30/20/10 Power domains REAL-TIME CLOCK BACKUP REGISTERS RESET/WAKE-UP CONTROL REGULATOR 32 kHz OSCILLATOR ALWAYS-ON/RTC POWER DOMAIN MAIN POWER DOMAIN RTCX1 VBAT VDDREG RTCX2 VDDIO VSS to memories, peripherals, oscillators, PLLs to core to I/O pads ADC DAC OTP ADC POWER DOMAIN OTP POWER DOMAIN USB0 POWER DOMAIN VDDA VSSA VPP USB0 USB0_VDDA3V3_DRIVER USB0_VDDA3V3 LPC18xx ULTRA LOW-POWER REGULATOR POWER SELECTOR ALARM RESET WAKEUP0/1/2/3 to RTC domain peripherals 002aag305 to RTC I/O pads (Vps) |
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