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ADS6123IRHB25 Datasheet(PDF) 21 Page - Texas Instruments |
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ADS6123IRHB25 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 67 page ![]() www.ti.com PIN CONFIGURATION (CMOS MODE) DRVDD AGND CLKP CLKM 1 2 3 4 5 6 7 8 NC NC RESET D5 SCLK D4 SDATA D3 SEN D2 D1 D0 24 23 22 21 20 19 18 17 BottomPadConnected ToDRGND ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 RHB PACKAGE (TOP VIEW) Figure 7. CMOS Mode Pinout Table 13. Pin Assignments – CMOS Mode PIN PIN NUMBER PIN NAME DESCRIPTION TYPE NUMBER OF PINS AVDD Analog power supply I 13, 15 2 AGND Analog ground I 6, 9, 12 3 CLKP, CLKM Differential clock input I 7, 8 2 INP, INM Differential analog input I 10, 11 2 Internal reference mode – common-mode voltage output. VCM External reference mode – reference input. The voltage forced on this pin sets the I/O 14 1 internal references. Serial interface RESET input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin, or by using RESET the software reset option. See the SERIAL INTERFACE section. I 2 1 In parallel interface mode, the user has to tie the RESET pin permanently HIGH. (SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100-k Ω pull-down resistor. This pin functions as serial interface clock input when RESET is low. When RESET is tied high, it controls the coarse gain and internal/external reference SCLK selection. Tie SCLK to low for internal reference and 0 dB gain and high for I 3 1 internal reference and 3.5 dB gain. See Table 1. The pin has an internal 100-k Ω pull-down resistor. This pin functions as serial interface data input when RESET is low. It controls various power down modes along with PDN pin when RESET is tied high. SDATA I 4 1 See Table 3 for detailed information. The pin has an internal 100 k Ω pull-down resistor. This pin functions as serial interface enable input when RESET is low. When RESET is high, it controls output interface type and data formats. See Table 2 for SEN I 5 1 detailed information. The pin has an internal 100-k Ω pull-up resistor to DRVDD. PDN Global power down control pin I 16 1 Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122 |
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