ADS6123IRHB25 datasheet(32/67 Pages) TI1

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fIN − Input Frequency − MHz

100

150

200

250

300

350

400

450

500

G043

Gain = 0 dB

Gain = 3.5 dB

fIN − Input Frequency − MHz

100

150

200

250

300

350

400

450

500

G044

Gain = 0 dB

Gain = 3.5 dB

fIN − Input Frequency − MHz

100

200

300

400

500

G045

Input adjusted to get −1dBFS input

1 dB

0 dB

5 dB

6 dB

2 dB

3 dB

4 dB

fIN − Input Frequency − MHz

100

200

300

400

500

G046

2 dB

5 dB

1 dB

0 dB

3 dB

4 dB

Input adjusted to get −1dBFS input

6 dB

DRVDD − Supply Voltage − V

100

102

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

G048

fIN = 10.1 MHz

AVDD = 3.3 V

SNR

SFDR

AVDD − Supply Voltage − V

3.0

3.1

3.2

3.3

3.4

3.5

3.6

G047

fIN = 70.1 MHz

DRVDD = 3.3 V

SNR

SFDR

ADS6125, ADS6124

ADS6123, ADS6122

SLAS560A – OCTOBER 2007 – REVISED MARCH 2008

TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS) (continued)

All plots are at 25

°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V

PP differential

clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output

interface (unless otherwise noted)

SFDR vs INPUT FREQUENCY (LVDS interface)

SNR vs INPUT FREQUENCY (LVDS interface)

Figure 50.

Figure 51.

SFDR vs INPUT FREQUENCY ACROSS GAINS

SINAD vs INPUT FREQUENCY ACROSS GAINS

Figure 52.

Figure 53.

PERFORMANCE vs AVDD

PERFORMANCE vs DRVDD

Figure 54.

Figure 55.

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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

ADS6123IRHB25 Datasheet(PDF) 32 Page - Texas Instruments

ADS6123IRHB25 Datasheet(HTML) 32 Page - Texas Instruments

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