ADS6123IRHB25 datasheet(8/67 Pages) TI1

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DIGITAL CHARACTERISTICS

(1)

ADS6125, ADS6124

ADS6123, ADS6122

SLAS560A – OCTOBER 2007 – REVISED MARCH 2008

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1 AVDD = 3.3 V

ADS6125/ADS6124

PARAMETER

TEST CONDITIONS

ADS6123/ADS6122

MIN

TYP

MAX

UNIT

DIGITAL INPUTS

PDN, SCLK, SEN & SDATA (2)

High-level input voltage

2.4

Low-level input voltage

0.8

High-level input current

µA

Low-level input current

–33

µA

Input capacitance

DIGITAL OUTPUTS

CMOS INTERFACE, DRVDD = 1.8 to 3.3 V

High-level output voltage

DRVDD

Low-level output voltage

Output capacitance inside the device, from

Output capacitance

each output to ground

DIGITAL OUTPUTS

LVDS INTERFACE, DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω

(3)

High-level output voltage

1375

Low-level output voltage

1025

Output differential voltage, |VOD|

225

350

VOS Output offset voltage, single-ended

Common-mode voltage of OUTP, OUTM

1200

Output capacitance inside the device, from

Output capacitance

either output to ground

(1)

All LVDS and CMOS specifications are characterized, but not tested at production.

(2)

SCLK & SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins,

analog voltage needs to be applied as per Table 1 & Table 2.

(3)

IO Refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.

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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

ADS6123IRHB25 Datasheet(PDF) 8 Page - Texas Instruments

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