MFRC63002R datasheet(61/118 Pages) NXP

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MFRC630

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Product data sheet

COMPANY PUBLIC

Rev. 3.1 — 6 September 2012

227531

61 of 118

NXP Semiconductors

MFRC630

Contactless reader IC

9.5.1 IRQ0 register

Interrupt request register 0.

9.5.2 IRQ1 register

Interrupt request register 1.

Table 51.

IRQ0 register (address 06h); reset value: 00h

Bit

Symbol

Set

Hi AlertIrq

Lo AlertIrq

IdleIrq

TxIrq

RxIrq

ErrIrq

RxSOF

Irq

Access

rights

wdy

Table 52.

IRQ0 bits

Bit

Symbol

Description

Set

1: writing a 1 to a bit position 6..0 sets the interrupt request

0: Writing a 1 to a bit position 6..0 clears the interrupt request

HiAlerIrq

Set, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert,

HiAlertIrq stores this event and can only be reset if Set is cleared.

LoAlertIrq

Set, when bit LoAlert in register Status1 is set. In opposition to LoAlert,

LoAlertIrq stores this event and can only be reset if Set is cleared

IdleIrq

Set, when a command terminates by itself e.g. when the Command changes

its value from any command to the Idle command. If an unknown command

is started, the Command changes its content to the idle state and the bit

IdleIRq is set. Starting the Idle command by the Controller does not set bit

IdleIRq.

TxIrq

Set, when data transmission is completed, which is immediately after the last

bit is sent.

RxIrq

Set, when the receiver detects the end of a data stream.

Note: This flag is no indication that the received data stream is correct. The

error flags have to be evaluated to get the status of the reception.

ErrIrq

Set, when the one of the following errors is set:

FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr

RxSOFlrq

Set, when a SOF or a subcarrier is detected

Table 53.

IRQ1 register (address 07h)

Bit

Symbol

Set

GlobalIrq

LPCD_Irq

Timer4Irq

Timer3Irq

Timer2Irq

Timer1Irq

Timer0Irq

Access

rights

wdy

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