Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

XTNETA1622DW Datasheet(PDF) 16 Page - Texas Instruments

Part # XTNETA1622DW
Description  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

XTNETA1622DW Datasheet(HTML) 16 Page - Texas Instruments

Back Button XTNETA1622DW Datasheet HTML 12Page - Texas Instruments XTNETA1622DW Datasheet HTML 13Page - Texas Instruments XTNETA1622DW Datasheet HTML 14Page - Texas Instruments XTNETA1622DW Datasheet HTML 15Page - Texas Instruments XTNETA1622DW Datasheet HTML 16Page - Texas Instruments XTNETA1622DW Datasheet HTML 17Page - Texas Instruments XTNETA1622DW Datasheet HTML 18Page - Texas Instruments XTNETA1622DW Datasheet HTML 19Page - Texas Instruments XTNETA1622DW Datasheet HTML 20Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 68 page
background image
TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64BIT PCIHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
timing requirements (see Figure 7)
NO.
MIN
MAX
UNIT
1
tsu(PIDSEL)
Setup time, PIDSEL high before PCLK
↑
7
ns
2
tsu(PAD)
Setup time, PAD31 − PAD0 valid before PCLK
↑
7
ns
3
tsu(PCBE)
Setup time, PCBE3 − PCBE0 valid before PCLK
↑
7
ns
4
tsu(PIRDY)
Setup time, PIRDY low before PCLK
↑
7
ns
5
th(PIDSEL)
Hold time, PIDSEL high after PCLK
↑
1
ns
6
th(PAD)
Hold time, PAD31 − PAD0 valid after PCLK
↑
2
ns
7
th(PCBE)
Hold time, PCBE3 − PCBE0 valid after PCLK
↑
1
ns
8
th(PIRDY)
Hold time, PIRDY low after PCLK
↑
1
ns
operating characteristics (see Figure 7)
NO.
MIN
MAX
UNIT
9
td(PAD)
Delay time, PCLK
↑ to PAD31−PAD0 valid
2
11
ns
10
td(PTRDY)
Delay time, PCLK
↑ to PTRDY↓
2
11
ns
11
td(PDEVSEL)
Delay time, PCLK
↑ to PDEVSEL↓
2
11
ns
PCLK
(input)
PIDSEL
(input)
PAD31−
PAD0
(I/O)
PFRAME
(input)
PCBE3−
PCBE0
(input)
PIRDY
(input)
PTRDY
(output)
PDEVSEL
(output)
Address
Bus Cmd
5
1
7
BE
3
Data
8
Address
Phase
6
2
4
10
Data Phase
9
11
Figure 7. TNETA1570 Read Operation (PCI SAR as Slave)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com