XTNETA1622DW datasheet(5/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

cell-segmentation interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

Segmentation cell available

SEGCLAV

(CMOS)

PHY mode

SEGCLAV (RXEMPTY/RXCLAV) indicates that a complete cell is available.

SEGCLAV

(CMOS)

ATM mode

SEGCLAV (TXENB) is active low when SEGDATA contains a valid byte.

Segmentation clock

SEGCLK

(TTL)

PHY mode

SEGCLK (RXCLK) is used to synchronize transfers on SEGDATA. SEGCLK is

sourced from the UTOPIA interface.

SEGCLK

(TTL)

ATM mode

SEGCLK (TXCLK) is used to synchronize transfers on SEGDATA. SEGCLK is

sourced from the ATMCLK.

Segmentation data

SEGDATA7 −

SEGDATA0

84 − 87,

89 − 92

(CMOS)

PHY mode

SEGDATA7 − SEGDATA0 (RXDATA) is byte-wide true data that is sourced by the

TNETA1570. SEGDATA7 is the MSB.

SEGDATA0

89 − 92

(CMOS)

ATM mode

SEGDATA7 − SEGDATA0 (TXDATA) is byte-wide true data that is sourced by the

TNETA1570. SEGDATA7 is the MSB.

Segmentation enable

SEGEN

(TTL)

PHY mode

SEGEN (RXENB) indicates that a valid byte will be sent during the next clock cycle.

SEGEN

(TTL)

ATM mode

SEGEN (TXFULL /TXCLAV) indicates that at least 1-byte SEGDATA will be

accepted.

Segmentation parity

SEGPAR

(CMOS)

PHY mode

SEGPAR (RXPAR) is the odd-parity bit over SEGDATA7 − SEGDATA0.

SEGPAR

(CMOS)

ATM mode

SEGPAR (TXPAR) is the odd-parity bit over SEGDATA7 − SEGDATA0.

Segmentation start of cell

SEGSOC

(CMOS)

PHY mode

SEGSOC (RXSOC) is active high when SEGDATA contains the first valid byte of

the cell.

SEGSOC

(CMOS)

ATM mode

SEGSOC (TXSOC) is active high when SEGDATA contains the first valid byte of

the cell.

high-priority segmentation (request and acknowledge)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

HPSREQ

109

(TTL)

High-priority segmentation request. HPSREQ is sampled at each new segmentation opportunity

and is synchronous to the PCI-bus clock. When HPSREQ is active, TNETA1570 initiates the

procedure for transmitting a cell from TX DMA channel 1. To ensure that the high-priority

segmentation request is processed, HPSREQ remains active until HPSACK is set low. HPSREQ

is deasserted within two PCI-bus clock cycles of when HPSACK is asserted.

HPSACK

108

(CMOS)

High-priority segmentation acknowledge. HPSACK is asserted for one PCI-bus clock cycle to

acknowledge that HPSREQ is detected.

XTNETA1622DW Datasheet(PDF) 5 Page - Texas Instruments

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