XTNETA1622DW datasheet(55/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

parity error (PERR) protocol (continued)

The TNETA1570 asserts PERR if the parity-error-response bit (bit 6) in the PCI-configuration-space command

after the cycle in which the error occurred. If a parity error is detected during a transfer involving the TNETA1570,

the transaction is allowed to complete unless the TNETA1570 is the master and a target disconnect is detected

(i.e. the TNETA1570 will not master abort due to a parity error).

system error (SERR) protocol

The TNETA1570 sets an internal SERR flag under any of the following conditions:

D If an address-parity error is detected on the PCI bus (even if the TDC1570 isnot the target of the transaction)

and the parity-error-response bit is set in the PCI-configuration-space command register.

D If the TNETA1570 detects PERR asserted while mastering the bus

D If the PCI-master-retry counter expires

D If the TNETA1570 receives a target abort (disconnect without retry) while mastering the bus

D If the TNETA1570 self selects

The TNETA1570 asserts SERR if the SERR enable bit (bit 8) in the PCI-configuration-space command register

is set and the internal system-error flag is set. The TNETA1570 halts and waits for software or hardware reset

after SERR is asserted.

The TNETA1570 sets the signaled-system error bit (bit 14) in the PCI-configuration-space status register when

SERR is asserted.

host-interrupt (INTA) protocol

The TDC1570 generates an interrupt to the host by asserting INTA if any of the bits in the internal status register

are set and the corresponding status-mask-register bit is also set.

PCI-to-UTOPIA data flow for segmentation unit

little-endian configuration

There are two scenarios for TNETA1570 cell-payload PCI reads from the host memory when the TNETA1570

is configured as a little-endian device. These are 32-bit PCI cell-payload reads and 64-bit PCI cell-payload

reads.

32-bit PCI cell-payload reads

The top-down order of the following chart represents the time order of 32-bit word reads by the TNETA1570.

PCI ADDRESS

PCI ADDRESS BITS

×10

×14

×18

The cell data above is transmitted from the segmentation unit’s UTOPIA bus in the byte order 0, 1, 2, 3, 4, 5, . . .

XTNETA1622DW Datasheet(PDF) 55 Page - Texas Instruments

XTNETA1622DW Datasheet(HTML) 55 Page - Texas Instruments

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