XTNETA1622DW datasheet(18/68 Pages) TI1

18 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

operating characteristics (see Figure 9)

NO.

MIN†

MAX†

UNIT

tw(CMWEL)

Pulse duration, CMWE low

td(CMWE)1

Delay time, CMAD17 − CMAD0 valid to CMWE

↓

td(CMWE)2

Delay time, CMDATA31 − CMDATA0 valid to CMWE

↑

td(CMDATA)

Delay time, CMWE

↑ to CMDATA31−CMDATA0 invalid

† These values are for full-duplex operation at 33 MHz.

CMOE

(output)

CMAD17 −

CMAD0

(output)

CMDATA31 −

CMDATA0

(output)

Valid

Invalid

CMWE

(output)

Figure 9. Control-Memory-Interface Write Operation

timing requirements (see Figure 10)

NO.

MIN†

MAX

UNIT

tsu(CMDATA)

Setup time, CMDATA31 − CMDATA0 valid before CMOE

↑

th(CMDATA)

Hold time, CMDATA31 − CMDATA0 valid after CMOE

↑

† These values are for full-duplex operation at 33 MHz.

operating characteristics (see Figure 10)

NO.

MIN

MAX

UNIT

td(CMOE)

Delay time, CMAD17 − CMAD0 valid to CMOE

↓

CMWE

(output)

CMAD17−

CMAD0

(output)

CMDATA31−

CMDATA0

(input)

Valid

CMOE

(output)

Figure 10. Control-Memory-Interface Read Operation

XTNETA1622DW Datasheet(PDF) 18 Page - Texas Instruments

XTNETA1622DW Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL