XTNETA1622DW datasheet(11/68 Pages) TI1

11 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

timing requirements (see Note 5 and Figure 2)

NO.

MIN

MAX

UNIT

tw(SEGCLKH)

Pulse duration, SEGCLK high

tw(SEGCLKL)

Pulse duration, SEGCLK low

tsu(SEGEN)

Setup time, SEGEN low before SEGCLK

↑

th(SEGEN)

Hold time, SEGEN low after SEGCLK

↑

NOTE 5: All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK.

operating characteristics (see Note 5 and Figure 2)

NO.

MIN

MAX

UNIT

td(SEGCLAV)

Delay time, SEGCLK

↑ to SEGCLAV↓

td(SEGSOC)

Delay time, SEGCLK

↑ to SEGSOC↑

td(SEGDATA)

Delay time, SEGCLK

↑ to SEGDATA7−SEGDATA0 valid

td(SEGPAR)

Delay time, SEGCLK

↑ to SEGPAR valid

NOTE 5: All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK.

SEGDATA7 −

SEGDATA0

(output)

SEGCLAV

(output)

SEGCLK

(input)

SEGSOC

(output)

SEGEN

(input)

Byte 1

Byte 2

Byte 3

Byte 49

Input

Ignored

Byte 50

Byte 48

Byte 51

SEGPAR

(output)

Figure 2. Segmentation-Cell Interface (PHY/ATM Low)

XTNETA1622DW Datasheet(PDF) 11 Page - Texas Instruments

XTNETA1622DW Datasheet(HTML) 11 Page - Texas Instruments

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