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XTNETA1622DW Datasheet(PDF) 13 Page - Texas Instruments

Part # XTNETA1622DW
Description  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE
PDF  68 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

XTNETA1622DW Datasheet(HTML) 13 Page - Texas Instruments

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TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64BIT PCIHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
13
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
timing requirements (see Note 5 and Figure 4)
NO.
MIN
MAX
UNIT
1
tw(SEGCLKH)
Pulse duration, SEGCLK high
10
ns
2
tw(SEGCLKL)
Pulse duration, SEGCLK low
10
ns
3
tsu(SEGEN)
Setup time, SEGEN high before SEGCLK
↑
10
ns
4
th(SEGEN)
Hold time, SEGEN high after SEGCLK
↑
1
ns
NOTE 5: All output signals are generated on the rising edge of SEGCLK. All input signals are sampled on the rising edge of SEGCLK.
operating characteristics (see Note 5 and Figure 4)
NO.
MIN
MAX
UNIT
5
td(SEGSOC)
Delay time, SEGCLK
↑ to SEGSOC↑
1
20
ns
6
td(SEGDATA)
Delay time, SEGCLK
↑ to SEGDATA7−SEGDATA0 valid
1
20
ns
7
td(SEGPAR)
Delay time, SEGCLK
↑ to SEGPAR↑
1
20
ns
8
td(SEGCLAV)1
Delay time, SEGCLK
↑ to SEGCLAV↑
1
20
ns
9
td(SEGCLAV)2
Delay time, SEGCLK
↑ to SEGCLAV↓
1
20
ns
NOTE 5: All output signals are generated on the rising edge of SEGCLK. All input signals are sampled on the rising edge of SEGCLK.
SEGDATA7−
SEGDATA0
(output)
SEGEN
(input)
SEGCLK
(input)
1
2
SEGSOC
(output)
4
3
5
6
SEGCLAV
(output)
8
Byte 53
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
If necessary
9
7
SEGPAR
(output)
Figure 4. Segmentation-Cell Interface (PHY/ATM High)



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