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TLK3114SCZPV Datasheet(PDF) 52 Page - Texas Instruments |
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TLK3114SCZPV Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 68 page  3−34 Table 3−32. PHY XS Status 1 Register (Register 4.1) BIT(S) NAME DESCRIPTION READ/WRITE 15:8 Reserved Read is ignored. Read-only 7 Local fault Logical OR of register 4.8, bits 10 and 11. Read-only 6:3 Reserved Read is ignored. Read-only 2 TX link status 1 = Link is up 0 = Link is down Latches low until read. Read-only 1:0 Reserved Read is ignored. Read-only Table 3−33. PHY XS Speed Ability Register (Register 4.4) BIT(S) NAME DESCRIPTION READ/WRITE 15:1 Reserved Read returns all 0s. Read-only 0 10G capable Read returns 1. Read-only Table 3−34. Devices in Package Register (Register 4.5) BIT(S) NAME DESCRIPTION READ/WRITE 15:6 Reserved Read is ignored. Read-only 5 DTE XS present 1 = Device is configured as a DTE XS. 0 = Device is configured as a PHY XS. Read-only 4 PHY XS present 1 = Device is configured as a PHY XS. 0 = Device is configured as a DTE XS. Read-only 3:1 Not applicable Read returns all 0s. Read-only 0 Clause 22 registers present Read returns 1. Read-only Table 3−35. 10G PHY XS Status 2 Register (Register 4.8) BIT(S) NAME DESCRIPTION READ/WRITE 15 Device present Read returns 1. Read-only 14 Device present Read returns 0. Read-only 13:12 Reserved Read is ignored. Read-only 11 Transmit local fault 1 = Transmit fault detected 0 = No transmit fault detected Latches high until read. Read-only 10 Receive local fault 1 = Receive fault detected 0 = No receive fault detected Latches high until read. Read-only 9:0 Reserved Read is ignored. Read-only Table 3−36. 10G PHY XGXS Lane Status Register (Register 4.24) BIT(S) NAME DESCRIPTION READ/WRITE 15:13 Reserved Read is ignored. Read-only 12 Lane alignment 1 = PHY XGXS transmit lanes aligned 0 = PHY XGXS transmit lanes not aligned Read-only 11:4 Reserved Read is ignored. Read-only 3 Lane D sync Lane D is synchronized. Read-only 2 Lane C sync Lane C is synchronized. Read-only 1 Lane B sync Lane B is synchronized. Read-only 0 Lane A sync Lane A is synchronized. Read-only MDIO registers 4.32768−4.32781 are analogous to registers 16−29. The following table cross references the appropriate register definition. |
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