TLK3114SCZPV datasheet(55/68 Pages) TI1

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3−37

3.28 Loopback Testing

The TLK3114SC device can provide a self-test function by enabling the internal loop-back path with the assertion of

LPENx for each channel, setting bit 14 (Loopback) of register 4.0 or 5.0, or by setting bit 3 (Loopback) of MDIO

channel configuration registers 17−20, 4.32769−4.32772, or 5.32769−5.32772. Enabling this terminal or bit causes

serial transmitted data to be routed internally to the receiver for that channel (see Figure 1−5). The parallel data output

can be compared to the parallel input data for that channel to provide functional verification. The external differential

output is held in a high-impedance state during the loop-back testing.

3.29 Power-On Reset

Upon application of minimum valid power, the TLK3114SC device generates an internal power-on reset. During the

power-on reset the receive data terminals RDx[0:9] are tri-stated and the recovered receive clock terminals RC[A−D]

are held low. The length of the power-on reset cycle is dependent upon the frequency of the reference clock,

RFCP/RFCN, but is less than 1 ms in duration.

3.30 Differences Between the TLK31x4Sx Devices

The TLK31x4Sx class of devices contain several differences. The TLK3114 series represents improvements in robust

performance across operating conditions. The TLK3114 device class, however, contains distinct several functional

improvements and extensions beyond those included in the TLK3104SA device. These differences are outlined in

Table 3−45.

Table 3−45. Comparison of TLK3104SA and TLK3114SC Devices

PARAMETER/FUNCTION

TLK3104SA

TLK3114SC

HSTL

Supports HSTL scaled to 1.8 V

Buffers optimized for 1.5-V HSTL, although they

still support 1.8-V scaled HSTL. See Section 3.10.

Comma detect

Comma detect on positive comma only

Comma detect on both positive and negative

commas. See Section 3.12.

Improved error reporting

LOS and decode errors reported as 0xFF

Enhanced reporting. See Table 3−6.

End-of-packet error detection and reporting

Not supported

Supported. See Section 3.14.

Local fault and remote fault detection and

reporting

Not supported

Supported. See Section 3.15.

IPG code generation and stripping

Not supported

Supported. See Section 3.18.

Clock tolerance compensation

Not supported

Supported. See Section 3.19.

Repeater mode

Not supported

Supported. See Section 3.23.

Power

Low power

Further reduced power

Serial receive

XAUI compliant

Improved signal tolerance

Terminal A1

TRSTN

ENABLE

Terminal U1

ENABLE

DADR0

Clause 45 MDIO

Not supported

Supported. See Section 3.25.

MDIO PHY/PRT address name

DVAD[0:4]

PADR[0:4]

MDIO DEV address specifier

Not supported

DADR0. See Section 3.25.

The ENABLE terminal on the TLK3104SA device is U1. On the TLK3114SC device the ENABLE terminal is terminal

A1. The TLK3114 devices are compatible with a design intended for the TLK3104SA device. The TLK3104SA design

would be required to pull U1 high and A1 high. If a TLK3114SC device was substituted then U1 would be ignored,

since only clause 22 MDIO transactions would be executed, and A1 would still be required to be high. Also, the JTAG

standard, IEEE 1149.1, specifies that TRSTN is optional as long as there is an ENABLE or reset terminal which

accomplishes the same task. The TLK3114 devices place ENABLE where the TLK3104SA device had TRSTN so

that JTAG function is unaffected.

MDIO register addresses have been renamed to better reflect terminology in IEEE 802.3ae clause 45. The name

changes do not reflect a functional change.

TLK3114SCZPV Datasheet(PDF) 55 Page - Texas Instruments

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