TLK3114SCZPV datasheet(11/68 Pages) TI1

11 / 68 page

1−5

MUX

8-B/10-B

Encoder

TDx[7:0]

Tx FIFO

KGENx

TDx[9:0]

TCx

TDx[9:0]

MUX

PRBS

Generator

Parallel to

Serial

Baud Clock

Multiplying Clock

Synthesizer

Baud Clock

Interpolator and

Clock Recovery

MUX

Recovered

Clock

Serial to

Parallel and

Comma Detect

8-B/10-B

Decoder-

PRBS

Verification

RDx[7:0]

MUX

KFLAGx

RDx[9:0]

MUX

TXxP

LPENx

PRBSEN

CODE

RFCN

RFCP

RCx

RCA

PSYNC

CODE

TXxN

RXxP

RXxN

Mode

Selector

CONFIG0

CONFIG1

CTC

SYNCEN

Figure 1−5. Block Diagram of Individual Channel

1.1

Features

•

Quad 3.125 Gbps per channel transceiver providing 10-Gbps data throughput

•

IEEE 802.3 10-Gbps Ethernet XGXS compliant including:

−

XGMII parallel interface to MAC and XAUI serial interfaces

−

Clock tolerance compensation with column add/drop

−

XAUI interpacket gap /A/, /K/, and /R/ code generation and stripping

−

Remote and local fault reporting on the XGMII as defined

•

MDIO interface

•

Selectable synchronized or independent channel operation

•

Selectable transmit-only, receiver-only, transceiver, and repeater functions

•

Selectable on-chip 8-b/10-b ENDEC

•

On-chip receive equalization

•

Receiver differential input thresholds 200 mVP-P

•

On-chip 100-

Ω differential receiver termination

TLK3114SCZPV Datasheet(PDF) 11 Page - Texas Instruments

TLK3114SCZPV Datasheet(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL