LPC4088 datasheet(48/123 Pages) NXP

48 / 123 page

LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

48 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

– Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision back-off and frame retransmission.

– Includes power management by clock switching.

– Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

• Physical interface:

– Attachment of external PHY chip through standard MII or RMII interface.

– PHY register access is available via the MIIM interface.

7.16 USB interface

Remark: The USB Device/Host/OTG controller is available on parts LPC4088/78/76. The

USB Device-only controller is available on part LPC4074/72.

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

See Section 13.1 for details on typical USB interfacing solutions.

7.16.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory, and a

DMA controller. The serial interface engine decodes the USB data stream and writes data

to the appropriate endpoint buffer. The status of a completed USB transfer or error

condition is indicated via status registers. An interrupt is also generated if enabled. When

enabled, the DMA controller transfers data between the endpoint buffer and the USB

RAM.

7.16.1.1

Features

• Fully compliant with USB 2.0 Specification (full speed).

• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

• Supports SoftConnect and GoodLink features.

• While USB is in the Suspend mode, the LPC408x/7x can enter one of the reduced

power modes and wake up on USB activity.

• Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints.

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