LPC4088 datasheet(86/123 Pages) NXP

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LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

86 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

[1]

Refers to SDRAM clock signal EMC_CLKx.

[2]

The data input set-up time has to be selected with the following margin:

tsu(D) + delay time of feedback clock  SDRAM access time  board delay time  0.

[3]

The data input hold time has to be selected with the following margin:

th(D) + SDRAM access time - board delay time - delay time of feedback clock  0.

[1]

The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All

delay times are incremental delays for each element starting from delay block 0. See the LPC408x/7x user

manual for details.

Fig 20. Dynamic external memory interface signal timing

002aah129

Tcy(clk)

EMC_CLKn

delay = 0

EMC_DYCSn,

EMC_RAS,

EMC_CAS,

EMC_WE,

EMC_CKEOUTn,

EMC_A[22:0],

EMC_DQMOUTn

th(Q)

th(D)

tsu(D)

EMC_D[31:0]

write

EMC_D[31:0]

read

td(QV)

th(x)

td(xV)

Table 18.

Dynamic characteristics: Dynamic external memory interface programmable

clock delays

CL =10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V.Values guaranteed by design.

Symbol

Parameter

Conditions

Min

Max

Unit

delay time

Programmable delay block 0 (CMDDLY

or CLKOUTnDLY bit 0 = 1)

[1] 0.1

0.2

Programmable delay block 1 (CMDDLY

or CLKOUTnDLY bit 1 = 1)

[1] 0.2

0.5

Programmable delay block 2 (CMDDLY

or CLKOUTnDLY bit 2 = 1)

[1] 0.5

1.3

Programmable delay block 3 (CMDDLY

or CLKOUTnDLY bit 3 = 1)

[1] 1.2

2.9

Programmable delay block 4 (CMDDLY

or CLKOUTnDLY bit 4 = 1)

[1] 2.4

6.0

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