LPC4088 datasheet(63/123 Pages) NXP

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LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

63 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

requirements. In addition, the peripheral power control allows shutting down the clocks to

individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all

dynamic power use in any peripherals that are not required for the application. Each of the

peripherals has its own clock divider which provides even better power control.

The integrated PMU (Power Management Unit) automatically adjusts internal regulators

to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep

power-down modes.

The LPC408x/7x also implement a separate power domain to allow turning off power to

the bulk of the device while maintaining operation of the RTC and a small set of registers

for storing data during any of the power-down modes.

7.36.4.1

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence other than re-enabling the clock to the ARM

core.

In Sleep mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

The DMA controller can continue to work in Sleep mode and has access to the peripheral

RAMs and all peripheral registers. The flash memory and the main SRAM are not

available in Sleep mode, they are disabled in order to save power.

Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.

7.36.4.2

Deep-sleep mode

In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Deep-sleep mode and the logic levels of chip pins remain static.

The output of the IRC is disabled but the IRC is not powered down to allow fast wake-up.

The RTC oscillator is not stopped because the RTC interrupts may be used as the

wake-up source. The PLL is automatically turned off and disconnected. The clock divider

registers are automatically reset to zero.

The Deep-sleep mode can be terminated and normal operation resumed by either a

Reset or certain specific interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power

consumption to a very low value. Power to the flash memory is left on in Deep-sleep

mode, allowing a very quick wake-up.

Wake-up from Deep-sleep mode can initiated by the NMI, External Interrupts EINT0

through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,

an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input

pin transition, or a Watchdog Timer time-out, when the related interrupt is enabled.

Wake-up will occur whenever any enabled interrupt occurs.

LPC4088 Datasheet(PDF) 63 Page - NXP Semiconductors

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