LPC4088 datasheet(53/123 Pages) NXP

53 / 123 page

LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

53 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

7.23.1 Features

• Quad SPI Flash Interface (SPIFI) interface to external flash.

• Transfer rates of up to SPIFI_CLK/2 bytes per second.

• Code in the serial flash memory can be executed as if it was in the CPU’s internal

memory space. This is accomplished by mapping the external flash memory directly

into the CPU memory space.

• Supports 1-, 2-, and 4-bit bidirectional serial protocols.

• Half-duplex protocol compatible with various vendors and devices.

• Supported by a driver library available from NXP Semiconductors.

7.24 SSP serial I/O controller

The LPC408x/7x contain three SSP controllers. The SSP controller is capable of

operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. Only a single master and a single slave can communicate on the bus

during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits

to 16 bits of data flowing from the master to the slave and from the slave to the master. In

practice, often only one of these data flows carries meaningful data.

7.24.1 Features

• Maximum SSP speed of 60 Mbit/s (master) or 10 Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

7.25 I2C-bus serial I/O controllers

The LPC408x/7x contain three I2C-bus controllers.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be

controlled by more than one bus master connected to it.

7.25.1 Features

• All I2C-bus controllers can use standard GPIO pins with bit rates of up to 400 kbit/s

(Fast I2C-bus). The I2C0-bus interface uses special open-drain pins with bit rates of

up to 400 kbit/s.

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