LPC4088 datasheet(68/123 Pages) NXP

68 / 123 page

LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

68 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

7.37.5 AHB multilayer matrix

The LPC408x/7x use an AHB multilayer matrix. This matrix connects the instruction

(I-code) and data (D-code) CPU buses of the ARM Cortex-M4 to the flash memory, the

main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these

memories. Additionally, the matrix connects the CPU system bus and all of the DMA

controllers to the various peripheral functions.

7.37.6 External interrupt inputs

The LPC408x/7x include up to 30 edge sensitive interrupt inputs combined with one level

sensitive external interrupt input as selectable pin function. The external interrupt input

can optionally be used to wake up the processor from Power-down mode.

7.37.7 Memory mapping control

The Cortex-M4 incorporates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

The vector table may be located anywhere within the bottom 1 GB of Cortex-M4 address

space. The vector table must be located on a 128 word (512 byte) boundary because the

NVIC on the LPC408x/7x is configured for 128 total interrupts.

7.38 Debug control

Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four

watch points.

Limiting values

Table 7.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol

Parameter

Conditions

Min

Max

Unit

VDD(3V3)

supply voltage (3.3 V)

external rail

2.4

3.6

VDD(REG)(3V3)

regulator supply voltage (3.3 V)

2.4

3.6

VDDA

analog 3.3 V pad supply voltage

0.5

+4.6

Vi(VBAT)

input voltage on pin VBAT

for the RTC

0.5

+4.6

Vi(VREFP)

input voltage on pin VREFP

0.5

+4.6

VIA

analog input voltage

on ADC related

pins

0.5

+5.1

input voltage

5 V tolerant digital

I/O pins;

VDD(3V3)  2.4V

[2]

0.5

+5.5

VDD(3V3)  0 V

0.5

+3.6

other I/O pins

[2][3]

0.5

VDD(3V3) +

0.5

IDD

supply current

per supply pin

100

ISS

ground current

per ground pin

100

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