LPC4088 datasheet(83/123 Pages) NXP

83 / 123 page

LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

83 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

[1]

Parameters are shown as RDn or WDn in Figure 17 as indicated in the Conditions column.

[2]

Parameters specified for 40 % of VDD(3V3) for rising edges and 60 % of VDD(3V3) for falling edges.

[3]

Tcy(clk) = 1/CCLK (see LPC408x/7x User manual).

[4]

Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).

[5]

After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.

[6]

End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).

tBLSLBLSH

BLS LOW to BLS HIGH time WR10; PB = 0 [3] (WAITWR  WAITWEN +

 T

cy(clk)  1.4

(WAITWR

 WAITWEN +

 T

cy(clk)  2.7

tBLSHEOW

BLS HIGH to end of write

time

WR11; PB = 0

[6]

[3]

1.3 + Tcy(clk)

2.2 + Tcy(clk)

tBLSHDNV

BLS HIGH to data invalid

time

WR12;

PB = 0

[3] 1.4 + Tcy(clk)

2.7 + Tcy(clk)

Table 15.

Dynamic characteristics: Static external memory interface …continued

CL =10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol

Parameter[1]

Conditions[1]

Min

Max

Unit

Fig 17. External static memory read/write access (PB = 0)

RD1

RD5

RD2

WR2

WR9

WR12

WR10

WR11

RD5

RD6

WR8

WR1

EOR

EOW

RD7

RD4

EMC_Ax

EMC_CSx

EMC_OE

EMC_BLSx

EMC_WE

EMC_Dx

002aag214

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