PXS20 Product Brief, Rev. 1

Features

Freescale Semiconductor

22

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Independent control of both edges of each PWM output

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Synchronization to external hardware or other PWM supported

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Double buffered PWM registers

— Integral reload rates from 1 to 16

— Half cycle reload capability

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Multiple ADC trigger events can be generated per PWM cycle via hardware

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Fault inputs can be assigned to control multiple PWM outputs

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Programmable filters for fault inputs

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Independently programmable PWM output polarity

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Independent top and bottom deadtime insertion

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Each complementary pair can operate with its own PWM frequency and deadtime values

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Individual software control for each PWM output

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All outputs can be forced to a value simultaneously

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PWMX pin can optionally output a third signal from each channel

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Channels not used for PWM generation can be used for buffered output compare functions

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Channels not used for PWM generation can be used for input capture functions

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Enhanced dual edge capture functionality

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Option to supply the source for each complementary PWM signal pair from any of the following:

— External digital pin

— Internal timer channel

— External ADC input, taking into account values set in ADC high- and low-limit registers

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DMA support

2.5.31

eTimer Module

The PXS20 provides three eTimer modules on the 257 MAPBGA device, and two eTimer modules on the

144 LQFP package. Six 16-bit general purpose up/down timer/counters per module are implemented with

the following features:

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Maximum clock frequency of 120 MHz

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Individual channel capability

— Input capture trigger

— Output compare

— Double buffer (to capture rising edge and falling edge)

— Separate prescaler for each counter

— Selectable clock source

— 0–100% pulse measurement

— Rotation direction flag (Quad decoder mode)

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Maximum count rate