Features

PXS20 Product Brief, Rev. 1

Freescale Semiconductor

17

2.5.19

System Timer Module (STM)

The STM implements the following features:

•

Up-counter with 4 output compare registers

•

The STM is replicated for each processor.

2.5.20

Software Watchdog Timer (SWT)

This module implements the following features:

•

Fault tolerant output

•

Safe internal RC oscillator as reference clock

•

Windowed watchdog

•

Program flow control monitor with 16-bit pseudorandom key generation

•

Allows a high level of safety (SIL3 monitor)

The SWT module is replicated for each processor.

2.5.21

Fault Collection and Control Unit (FCCU)

The FCCU module has the following features:

•

Redundant collection of hardware checker results

•

Redundant collection of error information and latch of faults from critical modules on the device

•

Collection of self-test results

•

Configurable and graded fault control

— Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode

entered)

— External reaction (failure is reported to the external/surrounding system via configurable

output pins)

2.5.22

System Integration Unit Lite (SIUL)

The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O

(GPIO), internal peripheral multiplexing, and system reset operation. The reset configuration block

contains the external pin boot configuration logic. The pad configuration block controls the static electrical

characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O

pins of the MCU.

The SIU provides the following features:

•

Centralized pad control on a per-pin basis

— Pin function selection

1.Open System Architecture